library verilog;
use verilog.vl_types.all;
entity S_Box_S4 is
    port(
        S_Box_S4_Input  : in     vl_logic_vector(6 downto 1);
        S_Box_S4_Select : in     vl_logic;
        S_Box_S4_Output : out    vl_logic_vector(4 downto 1);
        S_Box_S4_Finish_Flag: out    vl_logic;
        clk             : in     vl_logic
    );
end S_Box_S4;
